As a switching semiconductor device having a large-current capacity and low saturation voltage (low ON-state voltage), there is known an insulated gate bipolar transistor (IGBT) that is also called a conductivity modulation type transistor. As shown in FIG. 16, a known semiconductor structure of pnp type IGBT includes a p.sup.+ -type collector layer (minority carrier injected layer) having a rear surface connected to a collector electrode 1, n.sup.+ -type buffer layer 3 laminated on the collector layer 2, and an n.sup.- -type conductivity modulation layer (n base) 4 formed by epitaxial growth on the buffer layer 3. The semiconductor structure further includes a gate electrode 6 made of polysilicon and formed on the surface of the conductivity modulation layer 4 through a gate insulating film 5, p-type emitter layer (p base) 7 formed as a well in a surface of the conductivity modulation layer 4 by self alignment using the gate electrode 6 as a mask, n.sup.+ -type source region 9, and an aluminum emitter electrode 8 formed on the emitter layer 7.
In the IGBT having the above-described vertical DMOS structure, when a positive potential with respect to the emitter electrode 8 is applied to the gate electrode 6, an n channel as an inversion layer is formed in a surface of the p-type emitter layer 7 which provides a channel diffusion layer (back gate) right under the gate electrode 6. Through this channel, electrons (majority carriers of the n.sup.- -type conductivity modulation layer 4) are injected from the emitter electrode 8 and source region 9 into the conductivity modulating layer 4. In response to this, holes (minority carriers of the n.sup.- -type conductivity modulating layer 4) are injected from the collector layer 2 into the conductivity modulation layer 4, with a result of a rapid increase in the conductivity of the conductivity modulation layer 4. As a result, the pnp transistor is turned on, and large current flows through the transistor, to provide a low ON-state voltage (low collector-emitter voltage).
When a load is short-circuited, for example, hole current I.sub.H flowing into the emitter electrode 8 through the portion of the emitter layer 7 right under the source region 9 is rapidly increased, and the voltage drop due to the diffusion resistance (p base resistance) r.sub.B at the portion right under the source region 9 is increased. As a result, the pn junction between the p-type emitter layer 7 and the n.sup.+ -type source region 9 tends to be forward biased, resulting in latch-up of a parasitic transistor (npn-type transistor consisting of the n.sup.- -type conductivity modulation layer 4, p-type emitter layer 7 and the n.sup.+ -type source region 9). Thus, the known IGBT has low capability to withstand breakdown upon load short-circuiting (i.e. low ability to prevent latch-up).
To improve the ability to prevent latch-up, it is effective to lower the current amplification factor h.sub.FE of the parasitic npn-type transistor. To this end, the impurity concentration of the p-type emitter layer 7 or that of the n.sup.+ -type source region 9 needs to be lowered. If the impurity concentration of the p-type emitter layer 7 is lowered, however, the diffusion resistance rB in the emitter layer 7 is undesirably increased. If the impurity concentration of the n.sup.+ -type source region 9 is lowered, the contact resistance between the source region 9 and the emitter electrode 8 is increased.
In view of the above, a structure as shown in FIG. 17 has been proposed which is intended to enhance the ability to prevent latch-up upon load short-circuiting, for example. In the IGBT structure shown in FIG. 17(a), the emitter electrode 8 does not directly contact the stripe-like source region 9 which extends in the gate-width (channel-width) direction of the gate electrode 6, but is in 5 conductively contact with a plurality of branch portions 9a that extend like a comb from the source region 9, such that the diffusion resistance r.sub.s exists as a parasitic element in each narrowed branch portion 9a.
Thus, in the IGBT semiconductor structure in which the diffusion resistance r.sub.s is equivalently present between the source region 9 and the emitter electrode 8, even if the voltage drop due to the diffusion resistance r.sub.B increases with a rapid increase in the hole current I.sub.H flowing into the emitter electrode 8 through the portion of the emitter layer 7 right under the source region 9 upon load short-circuiting, for example, the voltage drop due to the diffusion resistance r.sub.s increases at the same time with a rapid increase in the electron current I.sub.E flowing through the source region 9. Due to the increases in the voltage drops due to both of the diffusion resistance r.sub.B, r.sub.S, the pn junction between the emitter layer 7 and the source region 9 is less likely to be forward biased, thus reducing the likelihood of latch-up of the parasitic npn-type transistor. Thus, the IGBT structure of FIG. 17(a) shows increased capability to withstand breakdown upon load short-circuiting.
In the IGBT structure as shown in FIG. 17(b), a plurality of mutually isolated source regions 9b are formed such that these regions 9b are spaced from each other in the gate-width (channel-width) direction of the gate electrode 6, and the emitter electrode 8 is formed to overlap these source regions 9b. In this locally disconnected channel structure, the emitter electrode 8 is not conducted to the channel right under the gate electrode 6 through the portions interposed between the source regions 9b, and thus the diffusion resistance r.sub.s exists as a parasitic element between the source regions 9b and the emitter electrode 8, as in the structure of FIG. 17(a). In this arrangement, the structure of FIG. 17(b) also shows improved capability to withstand breakdown upon load shortcircuiting, due to the concurrent increases in the voltage drops due to the diffusion resistance.
In the IGBT structures as shown in FIGS. 17(a), 17(b), however, there is a problem as described below. Namely, these structures are effective to improve the ability to prevent latch-up by rapidly increasing the voltage drop due to the diffusion resistance r.sub.s of the source region 9, where excess voltage is applied, for example, upon load short-circuiting. In the normal ON state (when no excess voltage is applied), however, electron current flows into the diffusion resistance r.sub.s, and the voltage drop due to the resistance is continued, with a result of an increased ON-state voltage (collector saturation voltage) V.sub.CE(sat), and increased ON-state loss.